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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9772A one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 14-bit, 160 msps txdac+ with 2 interpolation filter functional block diagram 14-bit dac 2 fir inter- polation filter edge- triggered latches clock distribution and mode select 2 /4 mux control filter control 1 /2 1 pll clock multiplier +1.2v reference and control amp AD9772A clkcom clkvdd mod0 mod1 reset plllock div0 div1 clk+ clk data inputs (db13... db0) sleep dcom dvdd acom avdd reflo pllcom lpf pllvdd i outa i outb refio fsadj zero stuff mux features single 3.0 v to 3.6 v supply 14-bit dac resolution and input data width 160 msps input data rate 67.5 mhz reconstruction passband @ 160 msps 74 dbc sfdr @ 25 mhz 2 interpolation filter with high- or low-pass response 73 db image rejection with 0.005 db passband ripple zero-stuffing option for enhanced direct if performance internal 2 /4 clock multiplier 250 mw power dissipation; 13 mw with power-down mode 48-lead lqfp package applications communication transmit channel w-cdma base stations, multicarrier base stations, direct if synthesis, wideband cable systems instrumentation product description the AD9772A is a single-supply, oversampling, 14-bit digital- to-analog converter (dac) optimized for baseband or if waveform reconstruction applications requiring exceptional dynamic range. manufactured on an advanced cmos process, it integrates a complete, low distortion 14-bit dac with a 2 digital interpolation filter and clock multiplier. the on-chip pll clock multiplier provides all the necessary clocks for the digital filter and the 14-bit dac. a flexible differential clock input allows for a single-ended or differential clock driver for optimum jitter performance. for baseband applications, the 2 digital interpolation filter provides a low-pass response, hence providing up to a threefold reduction in the complexity of the analog reconstruction filter. it does so by multiplying the input data rate by a factor of two while simultaneously suppressing the original upper in-band image by more than 73 db. for direct if applications, the 2 digital interpolation filter response can be reconfigured to select the upper in-band image (i.e., high-pass response) while suppress- ing the original baseband image. to increase the signal level of the higher if images and their passband flatness in direct if applications, the AD9772A also features a zero stuffing option in which the data following the 2 interpolation filter is upsampled by a factor of two by inserting midscale data samples. the AD9772A can reconstruct full-scale waveforms with band- widths as high as 67.5 mhz while operating at an input data rate of 160 msps. the 14-bit dac provides differential current outputs to support differential or single-ended applications. a segm ented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. the differential current outputs may be fed into a transformer or a differential op amp topology to obtain a single- ended output voltage using an appropriate resistive load. the on-chip bandgap reference and control amplifier are config- ured for maximum accuracy and flexibility. the AD9772A can be driven by the on-chip reference or by a variety of external reference voltages. the full-scale current of the AD9772A can be adjusted over a 2 ma to 20 ma range, thus providing addi- tional gain ranging capabilities. the AD9772A is available in a 48-lead lqfp package and specified for operation over the industrial temperature range of C40 c to +85 c. product highlights 1. a flexible, low power 2 interpolation filter supporting reconstruction bandwidths of up to 67.5 mhz can be config- ured for a low- or high-pass response with 73 db of image rejection for traditional baseband or direct if applications. 2. a zero-stuffing option enhances direct if applications. 3. a low glitch, fast settling 14-bit dac provides exceptional dynamic range for both baseband and direct if waveform reconstruction applications. 4. the AD9772A digital interface, consisting of edge- triggered latches and a flexible differential or single-ended clock input, can support input data rates up to 160 msps. 5. on-chip pll clock multiplier generates all of the inter- nal high-speed clocks required by the interpolation filter and dac. 6. the current output(s) of the AD9772A can easily be config- ured for various single-ended or differential circuit topologies. txdac+ is a registered trademark of analog devices, inc.
rev. a C2C AD9772A?pecifications dc specifications parameter min typ max unit resolution 14 bits dc accuracy 1 integral linearity error (inl) 3.5 lsb differential nonlinearity (dnl) 2.0 lsb monotonicity (12-bit) guaranteed over specified temperature range analog output offset error C0.025 +0.025 % of fsr gain error (without internal reference) C2 0.5 +2 % of fsr gain error (with internal reference) C5 1.5 +5 % of fsr full-scale output current 2 20 ma output compliance range C1.0 +1.25 v output resistance 200 k ? output capacitance 3 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 1 a reference input input compliance range 0.1 1.25 v reference input resistance (reflo = 3 v) 10 m ? small signal bandwidth 0.5 mhz temperature coefficients unipolar offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply avdd voltage range 3.1 3.3 3.5 v analog supply current (i avdd )3437ma analog supply current in sleep mode (i avdd ) 4.3 6 ma dvdd1, dvdd2 voltage range 3.1 3.3 3.5 v digital supply current (i dvdd1 + i dvdd2 )3740ma clkvdd, pllvdd 4 (pllvdd = 3.0 v) voltage range 3.1 3.3 3.5 v clock supply current (i clkvdd + i pllvdd )2530ma clkvdd (pllvdd = 0 v) voltage range 3.1 3.3 3.5 v clock supply current (i clkvdd ) 6.0 ma nominal power dissipation 5 253 272 mw power supply rejection ratio (psrr) 6 C avdd C0.6 +0.6 % of fsr/v power supply rejection ratio (psrr) 6 C dvdd C0.025 +0.025 % of fsr/v operating range C40 +85 c notes 1 measured at i outa driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external amplifier to drive any external load. 4 measured at f data = 100 msps and f out = 1 mhz, div1, div0 = 0 v. 5 measured with pll enabled at f data = 50 msps and f out = 1 mhz. 6 measured over a 3.0 v to 3.6 v range. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.)
rev. a C3C AD9772A dynamic specifications parameter min typ max unit dynamic performance maximum dac output update rate (f dac ) 400 msps output settling time (t st ) (to 0.025%) 11 ns output propagation delay 1 (t pd )17ns output rise time (10% to 90%) 2 0.8 ns output fall time (10% to 90%) 2 0.8 ns output noise (i outfs = 20 ma) 50 pa hz ac linearitybaseband mode spurious-free dynamic range (sfdr) to nyquist (f out = 0 dbfs) f data = 65 msps; f out = 1.01 mhz 82 dbc f data = 65 msps; f out = 10.01 mhz 75 dbc f data = 65 msps; f out = 25.01 mhz 73 dbc f data = 160 msps; f out = 5.02 mhz 82 dbc f data = 160 msps; f out = 20.02 mhz 75 dbc f data = 160 msps; f out = 50.02 mhz 65 dbc two-tone intermodulation (imd) to nyquist (f out1 = f out2 = C6 dbfs) f data = 65 msps; f out1 = 5.01 mhz; f out2 = 6.01 mhz 85 dbc f data = 65 msps; f out1 = 15.01 mhz; f out2 = 17.51 mhz 75 dbc f data = 65 msps; f out1 = 24.1 mhz; f out2 = 26.2 mhz 68 dbc f data = 160 msps; f out1 = 10.02 mhz; f out2 = 12.02 mhz 85 dbc f data = 160 msps; f out1 = 30.02 mhz; f out2 = 35.02 mhz 70 dbc f data = 160 msps; f out1 = 48.2 mhz; f out2 = 52.4 mhz 65 dbc total harmonic distortion (thd) f data = 65 msps; f out = 1.0 mhz; 0 dbfs C80 db f data = 78 msps; f out = 10.01 mhz; 0 dbfs C74 db signal-to-noise ratio (snr) f data = 65 msps; f out = 16.26 mhz; 0 dbfs 71 db f data = 100 msps; f out = 25.1 mhz; 0 dbfs 71 db adjacent channel power ratio (acpr) wcdma with 4.1 mhz bw, 5 mhz channel spacing if = 16 mhz, f data = 65.536 msps 78 dbc if = 32 mhz, f data = 131.072 msps 68 dbc four-tone intermodulation 15.6 mhz, 15.8 mhz, 16.2 mhz and 16.4 mhz at C12 dbfs 88 dbfs f data = 65 msps, missing center ac linearityif mode four-tone intermodulation at if = 70 mhz 68.1 mhz, 69.3 mhz, 71.2 mhz and 72.0 mhz at C20 dbfs 77 dbfs f data = 52 msps, f dac = 208 mhz notes 1 propagation delay is delay from clk input to dac update. 2 measured single-ended into 50 ? load. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.)
rev. a C4C AD9772A?pecifications digital specifications parameter min typ max unit digital inputs logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current * C10 +10 a logic 0 current C10 +10 a input capacitance 5 pf clock inputs input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v pll clock enabledfigure 1a input setup time (t s ), t a = 25 c 0.5 ns input hold time (t h ), t a = 25 c 1.0 ns latch pulsewidth (t lpw ), t a = 25 c 1.5 ns pll clock disabledfigure 1b input setup time (t s ), t a = 25 c C1.2 ns input hold time (t h ), t a = 25 c 3.2 ns latch pulsewidth (t lpw ), t a = 25 c 1.5 ns clk/plllock delay (t od ), t a = 25 c 2.8 3.2 ns plllock (v oh ), t a = 25 c 3.0 v plllock (v ol ), t a = 25 c 0.3 v * mod0, mod1, div0, div1, sleep, reset have typical input currents of 15 a. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) t s 0.025% 0.025% db0 db13 clk+ clk iouta or ioutb t h t lpw t pd t st figure 1a. timing diagrampll clock multiplier enabled t s db0 db13 0.025% 0.025% iouta or ioutb t od plllock clk+ clk t h t lpw t pd t st figure 1b. timing diagrampll clock multiplier dis abled
rev. a C5C AD9772A (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.) digital filter specifications parameter min typ max unit maximum input data rate (f data ) 150 msps digital filter characteristics passband width 1 : 0.005 db 0.401 f out /f data passband width: 0.01 db 0.404 f out /f data passband width: 0.1 db 0.422 f out /f data passband width: C 3 db 0.479 f out /f data linear phase (fir implementation) stopband rejection 0.606 f clock to 1.394 f clock 73 db group delay 2 21 input clocks impulse response duration C 40 db 36 input clocks C 60 db 42 input clocks notes 1 excludes sin(x)/x characteristic of dac. 2 defined as the number of data clock cycles between impulse input and peak of output response. specifications subject to change without notice. frequency dc to f data 0 140 0 1 0.1 output db 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 20 40 60 80 100 120 figure 2a. fir filter frequency responsebaseband mode time samples 1 0.4 0 5 normalized output 10 15 20 25 30 35 40 45 0.8 0.6 0.4 0.2 0 0.2 figure 2b. fir filter impulse responsebaseband mode table i. integer filter coefficients for interpolation filter (43-tap half-band fir filter) lower upper integer coefficient coefficient value h(1) h(43) 10 h(2) h(42) 0 h(3) h(41) C 31 h(4) h(40) 0 h(5) h(39) 69 h(6) h(38) 0 h(7) h(37) C 138 h(8) h(36) 0 h(9) h(35) 248 h(10) h(34) 0 h(11) h(33) C 419 h(12) h(32) 0 h(13) h(31) 678 h(14) h(30) 0 h(15) h(29) C 1083 h(16) h(28) 0 h(17) h(27) 1776 h(18) h(26) 0 h(19) h(25) C 3282 h(20) h(24) 0 h(21) h(23) 10364 h(22) 16384
rev. a AD9772A C6C absolute maximum ratings * parameter with respect to min max unit avdd, dvdd1-2, clkvdd, pllvdd acom, dcom, clkcom, pllcom C 0.3 +4.0 v avdd, dvdd1-2, clkvdd, pllvdd avdd, dvdd1-2, clkvdd, pllvdd C 4.0 +4.0 v acom, dcom1-2, clkcom, pllcom acom, dcom1-2, clkcom, pllcom C 0.3 +0.3 v refio, reflo, fsadj, sleep acom C 0.3 avdd + 0.3 v i outa , i outb acom C 1.0 avdd + 0.3 v db0 C db13, mod0, mod1, plllock dcom1-2 C 0.3 dvdd + 0.3 v clk+, clk C clkcom C 0.3 clkvdd + 0.3 v div0, div1, reset clkcom C 0.3 clkvdd + 0.3 v lpf pllcom C 0.3 pllvdd + 0.3 v junction temperature 125 c storage temperature C 65 +150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposu re to absolute maximum ratings for extended periods may affect device reliability. ordering guide temperature package package model range description option * AD9772Aast C 40 c to +85 c 48-lead lqfp st-48 ad9772eb evaluation board * st = thin plastic quad flatpack. thermal characteristic thermal resistance 48-lead lqfp ja = 91 c/w jc = 28 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9772A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a AD9772A C7C pin function descriptions pin no. mnemonic description 1, 2, 19, 20 dcom digital common 3 db13 most significant data bit (msb) 4 C 15 db12 C db1 data bits 1 C 12 16 db0 least significant data bit (lsb) 17 mod0 invokes digital high-pass filter response (i.e., half-wave digital mixing mode). active high. 18 mod1 invokes zero-stuffing mode. active high. note, quarter-wave digital mixing occurs with mod0 also set high. 23, 24 nc no connect, leave open 21, 22, 47, 48 dvdd digital supply voltage (2.8 v to 3.2 v) 25 plllock phase lock loop lock signal when pll clock multiplier is enabled. high indicates pll is locked to input clock. provides 1 clock output when pll clock multiplier is disabled. maximum fanout is one (i.e., <10 pf). 26 reset resets internal divider by bringing momentarily high when pll is disabled to synchronize internal 1 clock to the input data and/or multiple AD9772A devices. 27, 28 div1, div0 div1 along with div0 sets the pll s prescaler divide ratio (refer to table iii.) 29 clk+ noninverting input to differential cock. bias to midsupply (i.e., clkvdd/2). 30 clk C inverting input to differential clock. bias to midsupply (i.e., clkvdd/2). 31 clkcom clock input common 32 clkvdd clock input supply voltage (2.8 v to 3.2 v) 33 pllcom phase lock loop common 34 pllvdd phase lock loop (pll) supply voltage (3.1 v to 3.5 v). to disable pll clock multiplier, connect pllvdd to pllcom. 35 lpf pll loop filter node. this pin should be left as a no connect (open) unless the dac update rate is less than 10 msps, in which case a series rc should be connected from lpf to pllvdd as indicated on the evaluation board schematic. 36 sleep power-down control input. active high. connect to acom if not used. 37, 41, 44 acom analog common 38 reflo refer ence ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 39 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 f capacitor to acom when internal reference activated. 40 fsadj full-scale current output adjust 42 i outb complementary dac current output. full-scale current when all data bits are 0s. 43 i outa dac current output. full-scale current when all data bits are 1s. 45, 46 avdd analog supply voltage (2.8 v to 3.2 v) pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) sleep lpf pllvdd pllcom clkvdd clkcom clk dcom dcom (msb) db13 db12 db11 db10 db9 nc = no connect db8 db7 db6 db5 clk+ div0 div1 reset AD9772A db4 plllock dvdd dvdd avdd avdd acom i outa i outb acom fsadj refio reflo acom db3 db2 db1 (lsb) db0 mod0 mod1 dcom dcom dvdd dvdd nc nc
rev. a AD9772A C8C definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current -output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db). signal-to-noise ratio (snr) s/n is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. passband frequency band in which any input applied therein passes unattenuated to the dac output. stopband rejection the amount of attenuation of a frequency outside the passband applied to the dac, relative to a full-scale signal applied at the dac input within the passband. group delay number of input clocks between an impulse applied at the device input and peak dac output current. impulse response response of the device to an impulse applied to the input. adjacent channel power ratio (or acpr) a ratio in dbc between the measured power within a channel relative to its adjacent channel. pllclock multiplier edge- triggered latches 2 fir interpolation filter AD9772A 3.3v 3.3v from hp8644a signal generator 3.3v clkvdd clkcom clk+ 1 filter control mux control mod0 mod1 reset plllock div0 div1 pllcom lpf pllvdd i outa i outb refio fsadj reflo avdd acom dvdd dcom sleep zero stuff mux 14-bit dac 100 mini-circuits t1 1t 20pf 50 50 20pf 1.91k 0.1 f +1.2v reference and control amp awg2021 or dg2020 digital data ext. clock hp8130 pulse generator ch1 ch2 ext. input 2 /4 clk 1k 1k 1 /2 clock distribution and mode select to fsea30 spectrum analyzer figure 3. basic ac characterization test setup
rev. a C9C AD9772A f out mhz 0 60 100 120 20 0 amplitude dbm 40 80 40 60 80 100 20 out-of- band in-band tpc 1. single-tone spectral plot @ f data = 65 msps with f out = f data /3 frequency mhz 0 60 100 150 0 amplitude dbm 40 80 50 100 20 out-of- band in-band tpc 4. single-tone spectral plot @ f data = 78 msps with f out = f data /3 frequency mhz 0 60 100 300 50 0 amplitude dbm 40 80 100 150 200 250 20 out-of- band in-band tpc 7. single-tone spectral plot @ f data = 160 msps with f out = f data /3 12dbfs 0dbfs 6dbfs f out mhz 30 15 02025 10 5 90 sfdr dbc 85 80 75 70 65 60 55 50 tpc 2. in-band sfdr vs. f out @ f data = 65 msps f out mhz 90 30 15 0 sfdr dbc 85 80 75 70 65 60 55 50 20 25 10 5 12dbfs 0dbfs 35 6dbfs tpc 5. in-band sfdr vs. f out @ f data = 78 msps f out mhz 90 0 amplitude dbm 85 80 75 70 65 60 55 50 10 20 30 40 50 60 12dbfs 6dbfs 0dbfs tpc 8. in-band sfdr vs. f out @ f data = 160 msps typical ac characterization curves (avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, pll disabled.) f out mhz 70 30 15 0 sfdr dbc 65 60 55 50 45 40 35 30 20 25 10 5 12dbfs 0dbfs 6dbfs tpc 3. out-of-band sfdr vs. f out @ f data = 65 msps f out mhz 70 0 amplitude dbm 65 60 55 50 45 40 35 30 5 101520253035 12dbfs 6dbfs 0dbfs tpc 6. out-of-band sfdr vs. f out @ f data = 78 msps f out mhz 70 0 amplitude dbm 65 60 55 50 45 40 35 30 10 20 30 40 50 60 70 12dbfs 6dbfs 0dbfs tpc 9. out-of-band sfdr vs. f out @ f data = 160 msps
rev. a AD9772A C10C f out mhz 90 0 imd dbc 85 80 75 70 65 60 55 50 51015202530 3dbfs 0dbfs 6dbfs tpc 10. third order imd products vs. f out @ f data = 65 msps a out dbfs 90 20 imd dbc 85 80 75 70 65 60 10 50 f data = 160msps f data = 65msps f data = 78msps 15 tpc 13. third order imd products vs. a out @ f out = f dac /11 avdd volts 90 70 50 3.6 3.3 3.0 imd dbc 80 60 85 75 65 55 3.1 3.2 3.4 3.5 6dbfs 0dbfs 3dbfs tpc 16. third order imd products vs. avdd @ f out = 10 mhz, f dac = 320 msps f out mhz 90 0 imd dbc 85 80 75 70 65 60 55 50 5 1015202530 3dbfs 0dbfs 6dbfs 35 tpc 11. third order imd products vs. f out @ f data = 78 msps a out dbfs 90 20 imd dbc 85 80 75 70 65 60 10 50 f data = 160msps f data = 65msps f data = 78msps 15 55 50 tpc 14. third order imd products vs. a out @ f out = f dac /5 f dac mhz 90 25 snr dbc 85 80 75 70 65 60 125 175 75 55 50 pll off pll on, optimum div0/1 settings tpc 17. snr vs. f dac @ f out = 10 mhz f out mhz 90 0 imd dbc 85 80 75 70 65 60 55 50 10 20 30 40 50 60 70 3dbfs 0dbfs 6dbfs tpc 12. third order imd products vs. f out @ f data = 160 msps avdd volts 90 70 50 3.6 3.3 3.0 sfdr dbc 80 60 85 75 65 55 3.1 3.2 3.4 3.5 6dbfs 0dbfs 3dbfs tpc 15. sfdr vs. avdd @ f out = 10 mhz, f dac = 320 msps temperature c 90 40 sfdr dbc 85 80 75 70 65 60 080 20 55 50 f data = 160msps f data = 78msps f data = 65msps 20 40 60 tpc 18. in-band sfdr vs. tempera- ture @ f out = f data /11
rev. a AD9772A C11C functional description figure 4 shows a simplified block diagram of the AD9772A. the AD9772A is a complete, 2 oversampling, 14-bit dac that includes a 2 interpolation filter, a phase-locked loop (pll) clock multiplier and a 1.20 v bandgap voltage reference. while the AD9772A s digital interface can support input data rates as high as 160 msps, its internal dac can operate up to 400 msps, thus providing direct if conversion capabilities. the 14-bit dac provides two complementary current outputs whose full-scale current is determined by an external resistor. the AD9772A features a flexible, low jitter, differential clock input providing excellent noise rejection while accepting a sine wave input. an on-chip pll clock multiplier produces all of the necessary synchronized clocks from an external reference clock source. separate supply inputs are provided for each functional block to ensure optimum noise and distortion performance. a sleep mode is also included for power savings. 14-bit dac 2 fir inter- polation filter edge- triggered latches clock distribution and mode select 2 /4 mux control filter control 1 /2 1 pll clock multiplier +1.2v reference and control amp AD9772A clkcom clkvdd mod0 mod1 reset plllock div0 div1 clk+ clk data inputs (db13... db0) sleep dcom dvdd acom avdd reflo pllcom lpf pllvdd i outa i outb refio fsadj zero stuff mux figure 4. functional block diagram preceding the 14-bit dac is a 2 digital interpolation filter that can be configured for a low-pass (i.e., baseband mode) or high- pass (i.e., direct if mode) response. the input data is latched into the edge-triggered input latches on the rising edge of the differential input clock as shown in figure 1a and then interpo- lated by a factor of two by the digital filter. for traditional baseband applications, the 2 interpolation filter has a low-pass response. for direct if applications, the filter s response can be converted into a high-pass response to extract the higher image. the output data of the 2 interpolation filter can update the 14-bit dac directly or undergo a zero-stuffing process to increase the dac update rate by another factor of two . this action enhances the relative signal level and passband flatness of the higher images. digital modes of operation the AD9772A features four different digital modes of operation controlled by the digital inputs, mod0 and mod1. mod0 controls the 2 digital filter s response (i.e., low-pass or high- pass), while mod1 controls the zero-stuffing option. the selected mode as shown in table ii will depend on whether the application requires the reconstruction of a baseband or if signal. table ii. digital modes digital digital zero- mode mod0 mod1 filter stuffing baseband 0 0 low no baseband 0 1 low yes direct if 1 0 high no direct if 1 1 high yes applications requiring the highest dynamic range over a wide bandwidth should consider operating the AD9772A in a baseband mode. note, the zero-stuffing option can also be used in this mode although the ratio of signal to image power will be reduced. applications requiring the synthesis of if signals should con- sider operating the AD9772A in a direct if mode. in this case, the zero-stuffing option should be considered when synthesiz- ing and selecting ifs beyond the input data rate, f data . if the reconstructed if falls below f data , the zero-stuffing option may or may not be beneficial. note, the dynamic range (i.e., snr/sfdr) is also optimized by disabling the pll clock mul- tiplier (i.e., pllvdd to pllcom) and using an external low jitter clock source operating at the dac update rate, f dac . 2 interpolation filter description the 2 interpolation filter is based on a 43-tap half-band sym- metric fir topology that can be configured for a low- or high- pass response, depending on the state of the mod0 control input. the low-pass response is selected with mod0 low while the high-pass response is selected with mod0 high. the low -pass frequency and impulse response of the half-band interpolation filter are shown in figures 2a and 2b, while table i lists the idealized filter coefficients. note, a fir filter s impulse response is also represented by its idealized filter coefficients. the 2 interpolation filter essentially multiplies the input data rate to the dac by a factor of two, relative to its original input data rate, while simultaneously reducing the magnitude of the first image associated with the original input data rate occurring at f data C f fundamental . note, as a result of the 2 interpola- tion, the digital filter s frequency response is uniquely defined over its nyquist zone of dc to f data , with mirror images occur- ring in adjacent nyquist zones. the benefits of an interpolation filter are clearly seen in fig- ure 5, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to the 2 digital interpolation filter in a low-pass configuration. images of the sine wave signal appear around m ultiples of the dac s input data rate (i.e., f data ) as predicted by sampling theory. these undesirable images will also appear at the output of a reconstruction dac, although attenuated by the dac s sin(x)/x roll-off response. in many bandlimited applications, the images from the recon- struction process must be suppressed by an analog filter following the dac. the complexity of this analog filter is typically deter- mined by the proximity of the desired fundamental to the first image and the required amount of image suppression. adding to the complexity of this analog filter may be the requirement of compensating for the dac s sin(x)/x response.
rev. a AD9772A C12C referring to figure 5, the new first image associated with the dac s higher data rate after interpolation is pushed out fur- ther relative to the input signal, since it now occurs at 2 f data C f fundamental . the old first image associated with the lower dac data rate before interpolation is suppressed by the digital filter. as a result, the transition band for the analog reconstruction filter is increased, thus reducing the complexity of the analog filter. furthermore, the sin(x)/x roll-off over the original input data passband (i.e., dc to f data /2) is significantly reduced. as previously mentioned, the 2 interpolation filter can be converted into a high-pass response, thus suppressing the fun- damental while passing the original first image occurring at f data C f fundamental . figure 6 shows the time and frequency representation for a high-pass response of a discrete time sine wave. this action can also be modeled as a 1/2 wave digital mixing process in which the impulse response of the low-pass filter is digitally mixed with a square wave having a frequency of exactly f data /2. since the even coefficients have a zero value (refer to table i), this process simplifies into inverting the cen- ter coefficient of the low-pass filter (i.e., invert h(18)). note that this also corresponds to inverting the peak of the impulse response shown in figure 2a. the resulting high-pass frequency response becomes the frequency inverted mirror image of the low-pass filter response shown in figure 2b. it is worth noting that the new first image now occurs at f data + f fundamental . a reduced transition region of 2 f fundamental exists for image selection, thus mandating that the f fundamental be placed sufficiently high for practical filtering purposes in direct if applications. also, the lower sideband images occurring at f data C f fundamental and its multiples (i.e., n f data C f fundamental ) experience a frequency inversion while the upper sideband images occurring at f data + f fundamental and its mul- tiples (i.e., n f data + f fundamental ) do not. 2 2 f data f data dac 2 f data f data 1 st image suppressed 1 st image 2 f data f data f fundamental digital filter response new 1 st image 2 f data f data f fundamental frequency domain 1/ 2 f data 1/ f data time domain input data latch 2 interpolation filter dac's sin (x)/x response figure 5. time and frequency domain example of low-pass 2 digital interpolation filter 2 2 f data f data 2 f data f data 1 st image suppressed f fundamental 2 f data f data digital filter response upper and lower image 2 f data f data f fundamental frequency domain 1 / 2 f data 1/ f data time domain dac input data latch 2 interpolation filter dac's sin (x)/x response figure 6. time and frequency domain example of high-pass 2 digital interpolation filter
rev. a AD9772A C13C ?ero stuffing?option description as shown in figure 7, a zero or null in the frequency responses (after interpolation and dac reconstruction) occurs at the final dac update rate (i.e., 2 f data ) due to the dac s inherent sin(x)/x roll-off response. in baseband applications, this roll-off in the frequency response may not be as problematic since much of the desired signal energy remains below f data /2 and the amplitude variation is not as severe. however, in direct if applications interested in extracting an image above f data /2, this roll-off may be problematic due to the increased passband amplitude variation as well as the reduced signal level of the higher images. frequency f data 0 10 40 0 4 0.5 1 1.5 2 2.5 3 3.5 20 30 with zero-stuffing without zero-stuffing baseband region dbfs figure 7. effects of zero-stuffing on dacs sin(x)/x response for instance, if the digital data into the AD9772A represented a baseb and signal centered around f data /4 with a passband of f data /10, the reconstructed baseband signal out of the AD9772A would exp erience only a 0.18 db amplitude variation over its passband with the first image occurring at 7/4 f data with 17 db of attenuation relative to the fundamental. however, if the high- pass filter response was selected, the AD9772A would now produce pairs of images at [(2n + 1) f data ] f data /4 where n = 0, 1 . . .. note, due to the dac s sin(x)/x response, only the lower or upper sideband images centered around f data may be useful although they would be attenuated by C 2.1 db and C 6.54 db respectively, as well as experience a passband amplitude roll-off of 0.6 db and 1.3 db. to improve upon the passband flatness of the desired image and/or to extract higher images (i.e., 3 f data f fundamental ) the zero-stuffing option should be employed by bringing the mod1 pin high. this option increases the effective dac update rate by another factor of two since a midscale sample (i.e., 10 0000 0000 0000) is inserted after every data sample originating from the 2 interpolation filter. a digital multiplexer switching at a rate of 4 f data between the interpolation filter s output and a data register containing the midscale data sample is used to implement this option as shown in figure 6. hence, the dac output is now forced to return to its differential midscale current value (i.e., i outa C i outb ? 0 ma) after reconstructing each data sample from the digital filter. the net effect is to increase the dac update rate such that the zero in the sin(x)/x frequency response now occurs at 4 f data along with a corresponding reduction in output power as shown in figure 7. note that if the 2 interpolation filter s high-pass response is also selected, this action can be modeled as a 1/4 wave digital mixing process since this is equivalent to digitally mixing the impulse response of the low-pass filter with a square wave having a frequency of exactly f data (i.e., f dac /4). it is important to realize that the zero stuffing option by itself does not change the location of the images but rather their signal level, amplitude flatness and relative weighting. for instance, in the previous example, the passband amplitude flatness of the lower and upper sideband images centered around f data are improved to 0.14 db and 0.24 db respectively, while the signal level has changed to C 6.5 dbfs and C 7.5 dbfs. the lower or upper sideband image centered around 3 f data will exhibit an amplitude flatness of 0.77 db and 1.29 db with signal levels of approximately C 14.3 dbfs and C 19.2 dbfs. pll clock multiplier operation the phase lock loop (pll) clock multiplier circuitry along with the clock distribution circuitry can produce the necessary internally synchronized 1 , 2 , and 4 clocks for the edge triggered latches, 2 interpolation filter, zero stuffing multi- plier, and dac. figure 8 shows a functional block diagram of the pll clock multiplier, which consists of a phase detector, a charge pump, a voltage controlled oscillator (vco), a prescaler, and digital control inputs/outputs. the clock distribution circuitry generates all the internal clocks for a given mode of operation. the charge pump and vco are powered from pllvdd while the differential clock input buffer, phase detec tor, prescaler and clock distribution circuitry are powered from clkvdd. to ensure optimum phase noise performance from the pll clock multiplier and clock distribution circuitry, pllvdd and clkvdd must originate from the same clean analog supply. charge pump phase detector ext/int clock control prescaler clkvdd out1 clkcom mod1 mod0 reset clk+ lpf pll vdd dnc 2.7v to 3.6v pll com div1 div0 clock distribution + plllock clk vco AD9772A figure 8. clock multiplier with pll clock multiplier enabled the pll clock multiplier has two modes of operation. it can be enabled for less demanding applications providing a reference clock meeting the minimum specified input data rate of 6 msps. it can be disabled for applications below this data rate or for applications requiring higher phase noise performance. in this case, a reference clock at twice the input data rate (i.e., 2 f data ) must be provided without the zero stuffing option selected and four times the input data rate (i.e., 4 f data ) with the zero stuffing option selected. note, multiple AD9772A devices
rev. a AD9772A C14C can be synchronized in either mode if driven by the same reference clock, since the pll clock multiplier when enabled ensures synchronization. reset can be used for synchroniza- tion if the pll clock multiplier is disabled. figure 8 shows the proper configuration used to enable the pll clock multiplier. in this case, the external clock source is applied to clk+ (and/or clk C ) and the pll clock multiplier is fully enabled by connecting pllvdd to clkvdd. the settling/acquisition time characteristics of the pll are also dependent on the divide-by-n ratio as well as the input data rate. in general, the acquisition time increases with increasing data rate (for fixed divide-by-n ratio) or increasing divide-by-n ratio (for fixed input data rate). since the vco can operate over a 96 mhz C 400 mhz range, the prescaler divide-by-ratio following the vco must be set according to table iii for a given input data rate (i.e., f data ) to ensure optimum phase noise and successful locking. in general, the best phase noise performance for any prescaler setting is achieved with the vco operating near its maximum output frequency of 400 mhz. note, the divide-by-n ratio also depends on whether the zero stuffing option is enabled since this option requires the dac to operate at four times the input data rate. the divide-by-n ratio is set by div1 and div0. with the pll clock multiplier enabled, plllock serves as an active high control output which may be m onitored upon sys- tem power-up to indicate that the pll is successfully locked to the input clock. note, when the pll clock multiplier is not locked, plllock will toggle between logic high and low in an asynchronous manner until locking is finally achieved. as a result, it is recommended that plllock, if monitored, be sampled several times to detect proper locking 100 ms upon power-up. table iii. recommended prescaler divide-by-n ratio settings f data divide-by-n (msps) mod1 div1 div0 ratio 48 C 1600001 24 C 1000012 12 C 500104 6 C 250118 24 C 1001001 12 C 501012 6 C 251104 3 C 12.5 1 1 1 8 as stated earlier, applications requiring input data rates below 6 msps must disable the pll clock multiplier and provide an external reference clock. however, applications already contain- ing a low phase noise (i.e., jitter) reference clock that is twice ( or four times ) the input data rate should consider disabling the pll clock multiplier to achieve the best snr performance from the AD9772A. note that the sfdr performance and wideband noise performance of the AD9772A remains unaffected with or without the pll clock multiplier enabled. the effects of phase noise on the AD9772A s snr performance becomes more notice able at higher reconstructed output fre- quencies and signal levels. figure 9 compares the phase noise of a full-scale sine wave at exactly f data /4 at different data rates (hence carrier frequency) with the optimum div1, div0 setting. the effects of phase noise, and its effect on a signal s cnr performance, becomes even more evident at higher if fre- quencies as shown in figure 10. in both instances, it is the narrowband phase noise that limits the cnr performance. frequency offset mhz 0 10 110 0 noise density dbm/hz 30 50 70 90 12 3 4 5 100 80 60 40 20 pll off, f data = 50msps pll on, f data = 50msps pll on, f data = 75msps pll on, f data = 100msps pll on, f data = 160msps figure 9. phase noise of pll clock multiplier at exactly f out = f data /4 at different f data settings with optimum div0/div1 settings using r & s fsea30, rbw = 30 khz frequency mhz 10 10 110 120 amplitude dbm 30 50 70 90 122 124 126 128 130 figure 10. direct if mode reveals phase noise degrada- tion with and without pll clock multiplier (if = 125 mhz and f data = 100 msps) to disable the pll clock multiplier, connect pllvdd to pllcom as shown in figure 11. lpf may remain open since this portion of the pll circuitry is now disabled. the differen- tial clock input should be driven with a reference clock twice the data input rate in baseband applications and four times the data input rate in direct if applications in which the 1/4 wave mixing option is employed (i.e., mod1 and mod0 active high). the clock distribution circuitry remains enabled pro- viding a 1 internal clock at plllock. digital input data is
rev. a AD9772A C15C latched into the ad9772 on every other rising edge of the differ- ential clock input. the rising edge that corresponds to the input latch immediately precedes the rising edge of the 1 clock at plllock. adequate setup and hold time for the input data as shown in figure 1b should be allowed. note that enough delay is present between clk+/clk C and the data input latch to cause the minimum setup time for input data to be negative. this is noted in the digital specifications section. plllock contains a relatively weak driver output, with its output delay (t od ) sensitive to output capacitance loading. thus plllock should be buffered for fanouts greater than one, and/or load capacitance greater than 10 pf. if a data timing issue exists between the AD9772A and its external driver device, the 1 clock appearing at plllock can be inverted via an external gate to ensure proper setup and hold time. charge pump phase detector ext/int clock control prescaler clkvdd out1 clkcom mod1 mod0 reset clk+ lpf pll vdd pll com div1 div0 clock distribution + plllock clk vco AD9772A figure 11. clock multiplier with pll clock multiplier disabled synchronization of clk/data using reset with pll disabled the relationship between the internal and external clocks in this mode is shown in figure 12. a clock at the output update data rate (2 the input data rate) must be applied to the clk in- puts. i nternal dividers create the internal 1 clock necessary for the input latches. with the pll disabled, a delayed version of the 1 clock is present at the plllock pin. the dac latch is updated on the particular rising edge of the external 2 clock which corresponds to the rising edge of the 1 clock. updates to the input data should be synchronized to this specific rising edge as shown in figure 12. to ensure this synchronization, a logic 1 should be momentarily applied to the reset pin on power up, before clk is applied. applying a momentary logic 1 to reset brings the 1 clock at plllock to a logic 1. on the next rising edge of the 2 clock, the 1 clock will go to logic 0. the following rising edge of the 2 clock will cause the 1 clock to logic 1 again, as well as update the data in both of the input latches. digital data in external 2 clk delayed internal 1 clk load dependent delayed 1 clk at plllock i outa or i outb data t lpw t d t pd t pd data enters input latches on this edge figure 12. int ernal timing of AD9772A with pll disabled figure 13 illustrates the details of the reset function timing. reset going from a high to a low logic level enables the 1 clock output, generated by the plllock pin. if reset goes low at a time well before the rising edge of the 2 clock, then plllock will go high on the following edge of the 2 clock. if reset goes from a high to a low logic level 600 ps or later following the rising edge of the 2 clock, there will be a delay of one 2 clock cycle before plllock goes high. in either case, as long as reset remains low, plllock will change state on every rising edge of the 2 clock. as stated before, it is the rising edge of the 2 clock which immediately precedes the rising edge of plllock that latches data into the AD9772A input latches. ch1 2.00v ch2 2.00v m 10.0ns ch3 2.00v . [ t ] 1 2 3 t t t ch1 2.00v ch2 2.00v m 10.0ns ch4 1.20v ch3 2.00v b. figure 13. reset timing of AD9772A with pll disabled a.
rev. a AD9772A C16C dac operation the 14-bit dac along with the 1.2 v reference and reference control amplifier is shown in figure 14. the dac consists of a large pmos c urrent source array ca pable of providing up to 20 ma of full-scale current, i outfs . the array is divided into thirty-one equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose values are 1/16th of an msb current source. the remaining lsbs are binary weighted frac- tions of the middle-bits current sources. all of these current sources are switched to one or the other of two output nodes (i.e., i outa or i outb ) via pmos differential current switches. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dac s high output impedance. refio fsadj 250pf reflo avdd AD9772A r set 2k 0.1 f acom current source array i outa i outb interpolated digital data r load r load v diff = v outa v outb i outa i outb segmented switches lsb switches +1.2v ref 2.7v to 3.6v i ref figure 14. block diagram of internal dac, 1.2 v reference, and reference control circuits the full-scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set , as shown in figure 14. r set , in combination with both the reference control amplifier and voltage reference, refio, sets the reference current, i ref , which is mirrored to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is exactly thirty-two times the value of i ref . dac transfer function the AD9772A provides complementary current outputs, i outa and i outb . i outa will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 16383) while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as: i outa = ( dac code/ 16384) i outfs (1) i outb = (16383 C dac code )/16384 i outfs (2) where dac code = 0 to 16383 (i.e., decimal representation). as previously mentioned, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio , and external resistor, r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 ? or 75 ? cable. the single-ended voltage output appearing at the i outa and i outb nodes is simply: v outa = i outa r load (5) v outb = i outb r load (6) note that the full-scale value of v outa and v outb should not exceed the specified output compliance range of 1.25 v to pre- vent signal compression. to maintain optimum distortion and linearity performance, the maximum voltages at v outa and v outb should not exceed 500 mv p-p. the differential voltage, v diff , appearing across i outa and i outb , is: v diff = ( i outa ?i outb ) r load (7) substituting the values of i outa , i outb and i ref ; v diff can be expressed as: v diff = [(2 dac code C 16383)/16384] (32 r load / r set ) v refio (8) the last two equations highlight some of the advantages of operating the AD9772A differentially. first, the differential operation will help cancel common-mode error sources such as noise, distortion and dc offsets associated with i outa and i outb . second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the AD9772A can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relation- ship as shown in equation 8. reference operation the AD9772A contains an internal 1.20 v bandgap reference that can easily be disabled and overridden by an external reference. refio serves as either an output or input, depending on whether the internal or external reference is selected. if reflo is tied to acom, as shown in figure 15, the internal reference is activated, and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 f or greater from refio to reflo. if any additional loading is required, refio should be buffered with an external amplifier having an input bias cur- rent less than 100 na.
rev. a AD9772A C17C +1.2v ref refio fsadj current source array 250pf reflo avdd AD9772A 2k 0.1 f additional load optional external ref buffer 2.7v to 3.6v figure 15. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external 1.2 v reference such as the ad1580 may then be applied to refio as shown in figure 16. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compen- sation capacitor is not required since the internal reference is disabled, and the high input impedance of refio minimizes any loading of the external reference. +1.2v ref refio fsadj current source array 250pf reflo avdd AD9772A ad1580 2.7v to 3.6v reference control amplifier r set i ref = v refio /r set 10k v refio figure 16. external reference configuration reference control amplifier the AD9772A also contains an internal control amplifier that is used to regulate the dac s full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 16, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 a and 625 a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the ad9772 s dac, which is proportional to i outfs (refer to the power dissipation sec- tion). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. i ref can be controlled using the single-supply circuit shown in figure 17 for a fixed r set . in this example, the internal refer- ence is disabled, and the voltage of refio is varied over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply dac or digital potentiometer, thus allowing i ref to be digitally controlled for a fixed r set . this particular example shows the ad5220, an 8-bit serial input digital potenti- ometer, along with the ad1580 voltage reference. note, since the input impedance of refio does interact and load the digital potentiometer wiper to create a slight nonlinearity in the programmable voltage divider ratio, a digital potentiometer with 10 k ? or less of resistance is recommended. +1.2v ref refio fsadj current source array 250pf reflo avdd AD9772A ad1580 2.7v to 3.6v r set 10k 10k ad5220 1.2v figure 17. single-supply gain control circuit analog outputs the AD9772A produces two complementary current outputs, i outa and i outb , which may be configured for single-ended or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section, by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. figure 18 shows the equivalent analog output circuit of the AD9772A, consisting of a parallel combination of pmos differ- ential current switches associated with each segmented current source. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos s witches and is typically 200 k ? in parallel with 3 pf. due to the nature of a pmos device, the output impedance is also slightly dependent on the output voltage (i.e., v outa and v outb ) and, to a lesser extent, the analog supply voltage, avdd, and full-scale current, i outfs . although the output impedance s signal dependency can be a source of dc nonlinearity and ac lin earity (i.e., distortion), its effects can be limited if certain precautions are noted. i outa and i outb also have a negative and positive voltage compli- ance range. the negative output compliance range of C 1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9772A. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . operation beyond the positive compliance range will induce clipping of the output signal, which severely degrades the AD9772A s linearity and distortion performance. AD9772A avdd i outa r load r load i outb figure 18. equivalent analog output circuit
rev. a AD9772A C18C operating the AD9772A with reduced voltage output swings at i outa and i outb in a differential or single-ended output configu- ration reduces the signal dependency of its output impedance, thus enhancing distortion performance. although the voltage compliance range of i outa and i outb extends from C 1.0 v to +1.25 v, optimum distortion performance is achieved when the maximum full-scale signal at i outa and i outb does not exceed approximately 0.5 v. a properly selected transformer with a grounded center-tap will allow the AD9772A to provide the required power and voltage levels to different loads while main- taining redu ced voltage swings at i outa and i outb . dc-coupled applications requiring a differential or single-ended output con- figuration should size r load accordingly. refer to applying the AD9772A section for examples of various output configurations. the most significant improvement in the AD9772A s distortion and noise performance is realized using a differential output configuration. the common-mode error sources of both i outa and i outb can be substantially reduced by the common-mode rejection of a transformer or differential amplifier. these common- mode error sources include even-order distortion pr oducts and noise. the enhancement in distortion performance becomes more significant as the recons tructed waveform s frequency content increases and/or its amplitude decreases. the distor- tion and noise performance of the AD9772A is also dependent on the full-scale current setting, i outfs . although i outfs can be set between 2 ma and 20 ma, selecting an i outfs of 20 ma will provide the best distortion and noise performance. in summary, the AD9772A achieves the optimum distortion and noise performance under the following conditions: 1. positive voltage swing at i outa and i outb limited to 0.5 v. 2. differential operation. 3. i outfs set to 20 ma. 4. pll clock multiplier disabled note the majority of the ac characterization curves for the AD9772A are performed under the above-mentioned operating conditions. digital inputs/outputs the AD9772A consists of several digital input pins used for data, clock, and control purposes. it also contains a single digi- tal output pin, plllock, used to monitor the status of the internal pll clock multiplier or provide a 1 clock output. the 14-bit parallel data inputs follow standard positive binary coding where db13 is the most significant bit (msb), and db0 is the least significant bit (lsb). i outa produces a full-scale output current when all data bits are at logic 1. i outb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch and is designed to support an input data rate as high as 160 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth as shown in figures 1a and 1b. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met. the digital inputs (excluding clk+ and clk C ) are cmos-compatible with its logic thresholds, v threshold, set to approximately half the digital positive supply (i.e., dvdd or clkvdd) or v threshold = dvdd /2 ( 20%) the internal digital circuitry of the AD9772A is capable of operat- ing over a digital supply range of 2.8 v to 3.2 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh(max) . although a dvdd of 3.3 v will typically ensure proper compatibility with most ttl logic families, a series 200 ? resistors are recommended between the ttl logic driver and digital inputs to limit the peak current through the esd pro- tection diodes if v oh(max) exceeds dvdd by more than 300 mv. figure 19 shows the equivalent digital input circuit for the data and control inputs. digital input dvdd figure 19. equivalent digital input the AD9772A features a flexible d ifferential clock input oper- ating from separate supplies (i.e., clkvdd, clkcom) to achieve optimum jitter performance. the two clock inputs, clk+ and clk C , can be driven from a single-ended or differen- tial clock source. for single-ended operation, clk+ should be driven by a single-ended logic source while clk C should be set to the logic source s threshold voltage via a resistor divider/c apaci- tor network referenced to clkvdd as shown in figure 20. for differential operation, both clk+ and clk C should be biased to clkvdd/2 via a resistor divider network as shown in figure 21. an rf transformer as shown in figure 3 can also be used to convert a single-ended clock input to a differential clock input. r series v threshold AD9772A clk+ clkvdd clk clkcom 0.1 f 1k 1k figure 20. single-ended clock interface
rev. a AD9772A C19C AD9772A clk+ clkvdd clk clkcom 0.1 f 0.1 f 0.1 f 1k 1k 1k 1k ecl/pecl figure 21. differential clock interface the quality of the clock and data input signals are important in achieving the optimum performance. the external clock driver circuitry should provide the AD9772A with a low jitter clock input which meets the min/max logic levels while providing fast edges. although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain-bandwidth product of the AD9772A s differential comparator can tolerate sine wave inputs as low as 0.5 v p-p, with minimal degradation in its output noise floor. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low- value resistor network (i.e., 50 ? to 200 ? ) between the AD9772A digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. sleep mode operation the AD9772A has a sleep function that turns off the output current and reduces the analog supply current to less than 6 ma over the specified supply range of 2.8 v to 3.2 v. this mode can be activated by applying a logic level 1 to the s leep pin. the AD9772A takes less than 50 ns to power down and approximately 15 s to power back up. power dissipation the power dissipation, p d , of the AD9772A is dependent on several factors, including: 1. avdd, pllvdd, clkvdd, and dvdd, the power sup- ply voltages. 2. i outfs , the full-scale current output. 3. f data , the update rate. 4. the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs, and is insensitive to f data . conversely, i dvdd is dependent on both the digital input waveform and f data . figure 22 shows i dvdd as a function of full-scale sine wave output ratios (f out /f data ) for various update rates with dvdd = 3 v. the supply current from clkvdd and pllvdd is relatively insensitive to the digital input wave- form, but shown directly proportional to the update rate as shown in figure 23. ratio f out / f data 100 90 40 0.0 dvdd ma 80 70 60 50 0.1 0.2 0.3 0.4 0.5 30 20 10 0 f data = 160msps f data = 125msps f data = 100msps f data = 65msps f data = 50msps f data = 25msps figure 22. i dvdd vs. ratio @ dvdd = 3.3 v f data msps 25 0 0 i ma 20 15 10 5 50 100 150 200 i pllvdd i clkvdd figure 23. i pllvdd and i clkvdd vs. f data applying the AD9772A output configurations the following sections illustrate some typical output configura- tions for the AD9772A. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma for optimum performance. for applications requiring the optimum dynamic performance, a differential output configuration is highly recommended. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the trans- former configuration provides the optimum high-frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level-shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropriately -sized load resistor, r load , referred to acom. this configuration may be more suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting i outa or i outb into a negative unipolar voltage. this configuration pro- vides the best dc linearity since i outa or i outb is maintained at a virtual ground.
rev. a AD9772A C20C differential coupling using a transformer an rf transformer can be used to perform a differential -to- single-ended signal conversion as shown in figure 24. a differentially-coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer s passband. an rf transformer such as the mini-circuits t1-1t provides excellent rejec tion of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only and its linearity performance degrades at the low end of its frequency range due to core saturation. optional r diff r load mini-circuits t1-1t AD9772A i outa i outb figure 24. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the AD9772A. a differential resis- tor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive r econstruction filter or cable. r diff is determined by the transformer s impedance ratio and provides the proper source termination that results in a low vswr (voltage standing wave ratio). note that approximately half the signal power will be dissi- pated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion as shown in figure 25. the ad 9772a is configured with two equal load resistors, r load , of 25 ? . the differential voltage developed across i outa and i outb is converted to a single-ended signal via the differential op amp configura- tion. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amp s distortion performance by preventing the dac s high slewing output from overloading the op amp s input. AD9772A i outa i outb ad8055 c opt 25 25 225 225 500 500 figure 25. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8055 is configured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approximately 1.0 v. a high-speed amplifier, capable of preserving the differential performance of the AD9772A while meeting other system level objectives (i.e., cost, power), should be selected. the op amp s differential gain, its gain setting resistor values and full-scale output swing capa- bilities should all be considered when optimizing this circuit. the differential circuit shown in figure 26 provides the neces- sary level shifting required in a single-supply system. in this case, avdd, the positive analog supply for both the AD9772A and the op amp, is also used to level-shift the differential output of the AD9772A to midsupply (i.e., avdd/2). the ad8057 is a suitable op amp for this application. AD9772A i outa i outb ad8057 c opt 25 25 225 225 500 1k 1k avdd figure 26. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 27 shows the AD9772A configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly termi- nated 50 ? cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 ? . in this case, r load represents the equivalent load resistance seen by i outa . the unused output (i outb ) should be connected to acom directly. different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one addi- tional consideration in this mode is the integral nonlinearity (inl) as discussed in the analog output section of this data sheet. for optimum inl performance, the single-ended, buff- ered voltage output configuration is suggested. AD9772A i outa i outb 50 50 v outa = 0v to 0.5v i outfs = 20ma figure 27. 0 v to 0.5 v unbuffered voltage output single-ended buffered voltage output figure 28 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the AD9772A output current. u1 maintains i outa (or i outb ) at virtual ground, thus minimizing the nonlinear output impedance effect on the dac s inl performance as discussed in the analog output section. although this single-ended configuration typi- cally provides the best dc linearity performance, its ac distortion performance at higher dac update rates is often limited by u1 s slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of
rev. a AD9772A C21C r fb and i outfs . the full-scale output should be set within u1 s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. AD9772A i outa i outb u1 r fb 200 200 c opt i outfs = 10ma v out = i outfs r fb figure 28. unipolar buffered voltage output power and grounding considerations the AD9772A contains the five following power supply inputs: avdd, dvdd1, dvdd2, clkvdd and pllvdd. the AD9772A is specified to operate over a 2.8 v to 3.2 v supply range, thus accommodating 3.0 v and/or 3.3 v power supplies with up to 10% regulation. however, the following two condi- tions must be adhered to when selecting power supply sources for avdd, dvdd1 C dvdd2, clkvdd, and pllvdd: 1. pllvdd = clkvdd = 3.1 v C 3.5 v when pll clock multiplier enabled. (otherwise pllvdd = pllcom) 2. dvdd1 C dvdd2 = clkvdd 0.30 v to meet the first condition, pllvdd must be driven by the same power source as clkvdd with each supply input inde- pendently decoupled with a 0.1 f capacitor to its respective grounds. to meet the second condition, clkvdd can share the power supply source as dvdd1 C dvdd2, using the decoupling network shown in figure 29 to isolate digital noise from the sensitive clkvdd (and pllvdd) supply. alterna- tively, separate precision voltage regulators can be used to ensure that condition two is met. in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection, placement and routing and supply bypassing and grounding. figures 37 C 44 illustrate the recommended printed circuit board ground, power and signal plane layouts that are implemented on the AD9772A evaluation board. proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the AD9772A fea- tures separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. avdd, clkvdd, and pllvdd must be powered from a clean analog supply and decoupled to their respective analog common (i.e., acom, clkcom and pllcom) as close to the chip as physically possible. similarly, dvdd1 and dvdd2, the digital supplies, should be decoupled to dcom. for those applications requiring a single 3.3 v supply for both the analog, digital supply and phase lock loop supply, a clean avdd and/or clkvdd may be generated using the circuit shown in figure 29. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr-type electrolytic and tantalum capacitors. + 100 f electrolytic + 10 f 22 f tantalum 0.1 f ceramic avdd acom ttl/cmos logic circuits 3.0v or 3.3v power supply ferrite beads figure 29. differential lc filter for 3 v or 3.3 v maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9772A. if properly implemented, ground planes can perform a host of functions on high-speed circuit boards: bypassing, shielding current trans- port, etc. in mixed-signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference, and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous volt- age drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the pack- age as possible in order to minimize the sharing of conduction paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. the necessity and value of these resistors will be dependent upon the logic family used. for a more detailed discussion of the implementation and con- struction of high-speed, mixed-signal printed circuit boards, refer to analog devices application note an-333.
rev. a AD9772A C22C applications multicarrier the AD9772A s wide dynamic range performance makes it well suited for next generation base station applications in which it reconstructs multiple modulated carriers over a designated frequency band. cellular multicarrier and multimode radios are often referred to as software radios since the carrier tuning and modulation scheme is software programmable and performed digitally. the AD9772A is the recommended txdac in analog device s softcell chipset which comprises the ad6622, quadrature digital upconverter ic, along with its compan- ion rx digital downconverter ic, the ad6624, and 14-bit, 65 msps adc, the ad6644. figure 30 shows a generic soft- ware radio tx signal chain based on the AD9772A/ad6622. figure 31 shows a spectral plot of the AD9772A operating at 64.54 msps reconstructing eight is-136 modulated carriers spread over a 25 mhz band. for this particular test scenario, the AD9772A exhibited 74 dbc sfdr performance along with a carrier-to-noise ratio (cnr) of 73 db. figure 32 shows a spectral plot of the AD9772A operating at 52 msps reconstructing four equal gsm carriers spread over a 15 mhz band. the sfdr and cnr (in 100 khz bw) measured to be 76 dbc and 83.4 db respectively along with a channel power of C 13.5 dbfs. note, the test vectors were generated using rohde & schwarz s winiqsim software. jtag other ad6622s for increased channel capacity AD9772A plllock clk summation sport rcf cic filter nco qam sport rcf cic filter nco qam sport rcf cic filter nco qam sport rcf cic filter nco qam clk port ad6622 figure 30. generic multicarrier signal chain using the ad6622 and AD9772A frequency mhz 40 50 100 0 amplitude dbm 60 70 80 90 5101520 30 25 30 20 figure 31. spectral plot of AD9772A reconstructing eight is-136 modulated carriers @ f data = 64.54 msps, pllvdd = 0 frequency mhz 10 110 0 amplitude dbm 30 50 70 90 5 10 15 20 25 100 80 60 40 20 figure 32. spectral plot of AD9772A reconstructing four gsm modulated carriers @ f data = 52 msps, pllvdd = 0 although the above is-136 and gsm spectral plots are repre- sentative of the AD9772A s performance for a particular set of test conditions, the following recommendations are offered to maximize the performance and system integration of the AD9772A into multicarrier applications: 1. to achieve the highest possible cnr, the pll clock multi- plier should be disabled (i.e., pllvdd to pllcom) and the AD9772A s clock input driven with a low jitter/phase noise clock source at twice the input data rate. in this case, the divide-by-two clock appearing at plllock should serve as the master clock for the digital upconverter ic(s) such as the ad6622. plllock should be limited to a fanout of one. 2. the AD9772A achieves its optimum noise and distortion performance when configured for baseband operation along with a differential output and a full-scale current, i outfs , set to approximately 20 ma. 3. although the 2 interpolation filters frequency roll-off pro- vides a maximum reconstruction bandwidth of 0.422 f data, the optimum adjacent image rejection (due to the interpola- tion process) is achieved (i.e., > 73 dbc) if the maximum channel assignment is kept below 0.400 f data. 4. to simplify the subsequent if stages filter requirements (i.e., mixer image and lo rejection), it is often advantageous to offset the frequency band from dc to relax the transition band requirements of the if filter. 5. oversampling the frequency band often results in improved sfdr and cnr performance. this implies that the data input rate to the AD9772A is greater than f passband /0.4 where f passband is the maximum bandwidth in which the AD9772A will be required to reconstruct and place carriers. the improved noise performance results in a reduction in the txdac s noise spectral density due to the added process gain realized with oversampling. also, higher oversampling ratios provide greater flexibility in the frequency planning.
rev. a AD9772A C23C baseband single-carrier the AD9772A is also well suited for wideband single-carrier applications such as wcdma and multilevel qam whose modulation scheme requires wide dynamic range from the reconstruction dac to achieve the out-of-band spectral mask as well as the in-band cnr performance. many of these applica- tions strategically place the carrier frequency at one quarter of the dac s input data rate (i.e., f data /4) to simplify the digital modulator design. since this constitutes the first fixed if fre- quency, the frequency tuning is accomplished at a later if stage. to enhance the modulation accuracy as well as reduce the shape factor of the second if saw filter, many applications will often specify the passband of the if saw filter be greater than the channel bandwidth. the trade-off is that the txdac must now meet the particular application s spectral mask requirements within the extended passband of the 2nd if, which may include two or more adjacent channels. figure 33 shows a spectral plot of the AD9772A reconstructing a test vector similar to those encountered in wcdma applica- tions with the following exception. wcdma applications prescribe a root raised cosine filter with an alpha = 0.22, which limits the theoretical acpr of the txdac to about 70 db. this particular test vector represents white noise that has been band- limited by a brickwall bandpass filter with the same passband such that its maximum acpr performance is theoretically 83 db and its peak-to-rms ratio is 12.4 db. as figure 33 reveals, the AD9772A is capable of approximately 78 db acpr per- formance when one accounts for the additive noise/distortion contributed by the fsea30 spectrum analyzer. 30 center 16.25mhz span 6mhz 600khz dbm 40 50 60 70 80 90 100 110 120 130 c11 c11 c0 c0 cu1 cu1 figure 33. AD9772A achieves 78 db acpr performance reconstructing a wcdma-like test vector with f data = 65.536 msps and pllvdd = 0 direct if as discussed in the digital modes of operation section, the AD9772A can be configured to transform digital data represent- ing baseband signals into if signals appearing at odd multiples of the input data rate (i.e., n f data where n = 1, 3, . . .). this is accomplished by configuring the mod1 and mod0 digital inputs high. note, the maximum dac update rate of 400 msps limits the data input rate in this mode to 100 msps when the zero-stuffing operation is enabled (i.e., mod1 high). appli- cations requiring higher ifs (i.e., 140 mhz) using higher data rates should disable the zeros-stuffing operation. also, to minimize the effects of the pll clock multipliers phase noise as shown in figure 9, an external low jitter/phase noise clock source equal to 4 f data is recommended. figure 34 shows the actual output spectrum of the AD9772A reconstructing a 16-qam test vector with a symbol rate of 5 msps. the particular test vector was centered at f data /4 with f data = 100 msps, and f dac = 400 mhz. for many applica- tions, the pair of images appearing around f data will be more attractive since they have the flattest passband and highest signal power. higher images can also be used with the understanding that these images will have reduced passband flatness, dynamic range, and signal power, thus reducing the cnr and acp per- formance. figure 35 shows a dual tone sfdr amplitude sweep at the various if images with f data = 100 msps and f dac = 400 mhz and the two tones centered around f data /4. note, since an if filter is assumed to precede the AD9772A, the sfdr was measured over a 25 mhz window around the images occurring at 75 mhz, 125 mhz, 275 mhz, and 325 mhz. regardless of what image is selected for a given application, the adjacent images must be sufficiently filtered. in most cases, a saw filter providing differential inputs represents the optimum device for this purpose. for single-ended saw filters, a balanced- to-unbalanced rf transformer is recommended. the AD9772A s high output impedance provides a certain amount of flexibility in selecting the optimum resistive load, r load , as well as any matching network. frequency mhz 0 amplitude dbm 30 50 70 90 100 80 60 40 20 100 200 300 400 figure 34. spectral plot of 16-qam signal in direct if mode at f data = 100 msps
rev. a AD9772A C24C a out dbfs 90 85 60 14 sfdr (in 25mhz window) dbfs 80 75 70 65 12 10 8 6 2 4 0 55 50 325mhz 275mhz 75mhz 125mhz figure 35. dual-tone windowed sfdr vs. a out @ f data = 100 msps for many applications, the data update rate to the dac (i.e., f data ) must be some fixed integer multiple of some system reference clock (i.e., gsm C 13 mhz). furthermore, these applications prefer to use standard if frequencies which offer a large selection of saw filter choices of varying passbands (i.e., 70 mhz). these applications may still benefit from the AD9772A s direct if mode capabilities when used in conjunc- tion with a digital upconverter such as the ad6622. since the ad6622 can digitally synthesize and tune up to four modulated carriers, it is possible to judiciously tune these carriers in a region which may fall within an if filter s passband upon reconstruc- tion by the AD9772A. figure 36 shows an example in which four carriers were tuned around 18 mhz with a digital upcon- verter operating at 52 msps such that when reconstructed by the AD9772A in the if mode, these carriers fall around a 70 mhz if. frequency mhz 10 110 66 amplitude dbm 30 50 70 90 68 70 72 74 80 60 40 20 figure 36. spectral plot of four carriers at 60 mhz if with f data = 52 msps, pllvdd = 0 AD9772A evaluation board the ad9772-eb is an evaluation board for the AD9772A txdac. careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evalu- ate the AD9772A in different modes of operation. referring to figures 37 and 38, the AD9772A s performance can be evaluated differentially or single-endedly using a trans- former, differential amplifier, or directly coupled output. to evaluate the output differentially using the transformer, remove jumpers jp12 and jp13 and monitor the output at j6 (iout). to evaluate the output differentially, remove the transformer (t2) and install jumpers jp12 and jp13. the output of the amplifier can be evaluated at j13 (ampout). to evaluate the AD9772A single-endedly and directly coupled, remove the transformer and jumpers (jp12 and jp13) and install resistors r16 or r17 with 0 ? . the digital data to the AD9772A comes across a ribbon cable which interfaces to a 40-pin idc connector. proper termination or voltage scaling can be accomplished by installing rn2 and/or rn3 sip resistor networks. the 22 ? dip resistor network, rn1, must be installed and helps reduce the digital data edge rates. a single-ended clock input can be supplied via the ribbon cable by installing jp8 or more preferably via the sma connector, j3 (clock). if the clock is s upplied by j3, the AD9772A can be configured for a differential clock interface by installing jumpers jp1 and configuring jp2, jp3, and jp9 for the df position. to configure the AD9772A clock input for a single- ended clock interface, remove jp1 and configure jp2, jp3 and jp9 for the se position. the AD9772A s pll clock multiplier can be disabled by con- figuring jumper jp5 for the l position. in this case, the user must supply a clock input at twice (2 ) the data rate via j3 (clock). the 1 clock is made available on sma con- nector j1 (plllock), and should be used to trigger a pattern generator directly or via a programmable pulse generator. note that plll ock is capable of providing a 0 v to 0.85 v output into a 50 ? load. to enable the pll clock multiplier, jp5 must be configured for the h position. in this case, the clock may be supplied via the ribbon cable (i.e., jp8 installed) or j3 (clock). the divide-by-n ratio can be set by configuring jp6 (div0) and jp7 (div1). the AD9772A can be configured for baseband or direct if mode operation by configuring jumpers jp11 (mod0) and jp10 (mod1). for baseband operation, jp10 and jp11 should be configured in the l position. for direct if operation, jp10 and jp11 should be configured in the h position. for direct if operation without zero-stuffing, jp11 should be configured in the h position while jp10 should be configured in the low position. the AD9772A s voltage reference can be enabled or disabled via jp4 (ext ref in). to enable the reference, configure jp in the int position. a voltage of approximately 1.2 v will appear at the tp6 (refio) test point. to disable the internal refer- ence, configure jp4 in the ext position and drive tp6 with an external voltage reference. lastly, the AD9772A can be placed in the sleep mode by driving the tp11 test point with logic level high input signal.
rev. a AD9772A C25C 2 p1 1 p1 11 6 10 7 9 8 12 5 13 4 14 3 15 2 16 1 in13 4 p1 3 p1 in12 6 p1 5 p1 in11 8 p1 7 p1 in10 10 p1 9 p1 in9 12 p1 11 p1 in8 14 p1 13 p1 in7 16 p1 15 p1 in6 6 7 8 5 4 3 2 1 msb db13 db12 db11 db10 db9 db8 db7 9 10 db6 rn2 value rn1 value 6 7 8 5 4 3 2 1 msb in13 in12 in11 in10 in9 in8 in7 9 10 in6 rn3 value 18 p1 17 p1 11 6 10 7 9 8 12 5 13 4 14 3 15 2 16 1 in5 20 p1 19 p1 in4 22 p1 21 p1 in3 24 p1 23 p1 in2 26 p1 25 p1 in1 28 p1 27 p1 in0 30 p1 29 p1 32 p1 31 p1 6 7 8 5 4 3 2 1 db5 db4 db3 db2 db1 db0 clock 9 10 reset rn5 value rn4 value 6 7 8 5 4 3 2 1 in5 in4 in3 in2 in1 in0 inclock 9 10 inreset rn6 value lsb lsb 34 p1 33 p1 36 p1 35 p1 38 p1 37 p1 40 p1 39 p1 inclock inreset l1 1 fbead 2 dvdd_in 1 j7 c13 10 f 10v red dvdd tp22 dgnd 1 j8 blk tp23 red avdd tp24 c14 10 f 10v l2 1 fbead 2 avdd_in 1 j9 agnd 1 j10 blk tp25 red clkvdd tp26 l3 1 fbead 2 clkvdd_in 1 j11 c15 10 f 10v blk tp27 clkgnd 1 j12 c in +in u2 v +v ad8055 r15 500 4 7 2 3 out 6 1 2 j13 ampout c18 0.1 f c17 0.1 f blk tp19 red tp20 +v s v s r14 500 r12 500 r4 500 r11 50 r13 50 c16 100pf jp13 amp-b jp12 amp-a ia ib figure 37. drafting schematic of evaluation board
rev. a AD9772A C26C 36 34 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier u1 AD9772A msb db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 dvdd c8 0.1 f c7 0.1 f tp14 tp15 red blk ia ib reflo c6 1 f c5 0.1 f avdd red tp16 blk tp17 wht tp5 wht tp6 refio fsadj c4 0.1 f r10 1.91k r6 50 tp11 sleep wht reflo int ref a b 1 2 3 jp4 ext ref avdd clk clk+ div0 div1 pll-lock lpf 35 33 r5 val c1 val pllvdd note: shield around r5, c1 connected to pllvdd c c9 1 f c10 0.1 f clkvdd a b 1 2 3 jp6 a b 1 2 3 jp5 a b 1 2 3 jp7 clkvdd red tp7 reset tp10 wht db3 db2 db1 lsb db0 tp1 wht mod0 c a b 1 2 3 jp11 h l h l a b 1 2 3 jp10 dvdd dgnd mod1 tp2 wht c11 0.1 f c12 1 f dvdd tp3 wht tp4 wht 1 2 c j1 tp28 wht connect gnds as shown under using bottom signal layer c c note: locate all decoupling caps (c5 c12) as close as possible to dut, preferably under dut on bottom signal layer. jp8 edge clock a b 1 2 3 jp3 se df df clkvdd r2 1k c r3 1k c19 0.1 f a b 1 2 3 jp2 t1 1 2 3 s se p 6 4 c jp1 df 1 2 c clock j3 wht tp12 a b 1 2 3 jp9 df se r1 50 c t2 3 2 1 s p 4 6 r17 val r16 val 1 2 j6 iout r8 50 c3 10pf ia r9 opt ib c2 10pf r7 50 figure 38. drafting schematic of evaluation board (continued)
rev. a AD9772A C27C figure 39. silkscreen layertop figure 40. component side pcb layout (layer 1)
rev. a AD9772A C28C figure 41. ground plane pcb layout (layer 2) figure 42. power plane pcb layout (layer 3)
rev. a AD9772A C29C figure 43. solder side pcb layout (layer 4) figure 44. silkscreen layerbottom
rev. a AD9772A C30C 48-lead thin plastic quad flatpack (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm).
rev. a AD9772A C31C revision history location page data sheet changed from rev. 0 to rev. a. edits to digital specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 change to tpc 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 change to figure 9 captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 change to figure 13a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
C32C c02253C0C03/02(a) printed in u.s.a.

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